1. Field of the Invention
The present invention generally relates to input circuits and, more particularly, to a complementary input circuit with a nonlinear front end that is used to transfer the state of an external input to the internal signal lines of an integrated circuit chip.
2. Description of the Prior Art
A number of circuits are known in the prior art for converting bipolar logic levels, such as those produced by transistor-transistor logic (TTL) circuits, to field effect transistor (FET) logic levels. The need for such converter circuits arises because both TTL and FET circuits are used in modern data processing systems. For example, static and dynamic random access memories (RAMs) are typically fabricated with FETs in an integrated circuit form and have advantages of dense integration and low power dissipation. Bipolar logic circuits, however, have higher operating speed and are therefore frequently used for the control logic circuits for the main memories. Thus, there is a continuing need for improved interfaces between bipolar and FET circuits to overcome otherwise incompatible logic voltage levels.
Representative prior patents and publications are listed hereinbelow to indicate the state of the art.
U.S. Pat. No. 4,441,039 issued Apr. 3, 1984, to Schuster, entitled "Input Buffer for Semiconductor Memory", discloses an address input buffer for a cross-coupled latch of the type including two switching transistors. The address input buffer circuit includes a first depletion device having its source electrode connected to one latch node and the address input voltage connected to its gate. A second depletion device has its source electrode connected to the other latch node and to its gate. The voltage differential across the latch is a function of the variable current difference between the two depletion devices because the gate to source voltage of one depletion device is constant and the gate to source voltage of the other depletion device is variable in accordance with the level of the address input voltage. Thus, the address input voltage is not compared with a fixed reference voltage, and no capacitive boosting of a reference and address voltage is necessary to turn on the latch.
U.S. Pat. No. 4,418,401 issued Nov. 29, 1983 to Bansal, entitled "Latent Image RAM Cell", shows a partially cross-coupled RAM cell which will have a predictable initial storage state when pulsed drain voltage is turned on and, yet after the initial turn-on interval, will operate in a symmetric fashion storing either binary ones or zeros.
U.S. Pat. No. 4,406,956 issued Sept. 27, 1983 to Clemen et al, entitled "FET Circuit for Converting TTL to FET Logic Levels", shows a level converter circuit having first and second field effect transistors having their source and gate electrodes connected in common. The bipolar input signal is received at the common source connection while the gate electrodes receive a fixed reference potential that is equal to the threshold voltage plus the lowest possible high binary level of the bipolar input logic. The drain electrode of the first FET is connected to the output terminal of the level converter and the source electrode of a source follower FET. The drain electrode of the second FET is connected to a load device and to the gate of the source follower FET.
IBM Technical Disclosure Bulletin by Bernstein et al, entitled "TTL to FET Logic Level Converter", vol. 22, no. 8B, Jan. 1980, pp. 3751-2, shows an FET which receives an input signal and functions as a comparator using a reference voltage. The threshold voltage considerations for the input FET are diminished by applying a gate voltage that equals the desired reference voltage plus the threshold voltage of a second FET that is on the same chip as the input FET.